1. Field of the Invention
Example embodiments of the present invention relate to a composition for removing an insulation material, a method of removing an insulation layer and a method of recycling a substrate using the same. More particularly, example embodiments of the present invention relate to a composition for removing an insulation material that may effectively remove a low-k film and a passivation film without damaging a substrate, and to methods of removing an insulation layer and recycling a substrate using the composition.
A claim of priority under 35 USC §119 is made to Korean Patent Application No. 2005-97372, filed on Oct. 17, 2005, the contents of which are herein incorporated by reference in their entirety.
2. Description of the Related Art
Semiconductor devices having high integration degrees and rapid response speeds are desired as information processing apparatuses have been developed. Hence, the technology of manufacturing semiconductor devices has progressed to improve integration degrees, reliability and response speeds of the semiconductor devices.
As the integration degree increases, a design rule of the semiconductor device has been reduced. For example, a wiring having a width of about 100 nm or less has been developed. As the design rule of the semiconductor device is reduced, a RC delay time of the wiring has increased. The RC delay time is determined by a resistance (R) of the wiring and a capacitance (C) of an insulation layer between the wirings. An increase in the RC delay time shortens the response time. Therefore, reducing the resistance of the wiring or a dielectric constant (k) of the insulation layer is required for obtaining a semiconductor device having high integration degree and rapid response time.
In order to reduce the resistance of the wiring, a conductive material having a low resistivity has been developed. For example, a process of forming a wiring using copper having a resistivity which is substantially lower than that of aluminum has been developed.
In order to reduce the dielectric constant of the insulation layer, an insulation material having a low dielectric constant is required. In a conventional semiconductor device, the insulation layer is generally formed using silicon oxide having a dielectric constant of about 3.9. As a thickness of the insulation layer is reduced, the insulation layer formed using silicon oxide does not effectively isolate adjacent wirings from each other, and a parasitic capacitance between the adjacent wirings increases. Therefore, low-k materials having a dielectric constant which is substantially lower than that of silicon oxide have been developed in the semiconductor manufacturing industry.
The low-k material generally has a dielectric constant lower than or equal to about 3. Low-k materials are largely divided into organic low-k materials and inorganic low-k materials. However, organic low-k materials are primarily used. Examples of the organic low-k material include carbon-doped silicon oxide (SiOCH), silicon oxycarbide (SiOC), hydrogenated silicon oxide (SiOH), black diamond, methylsilsesquioxane (MSQ), fluorinated silicate glass (FSG) and organic silicate glass (OSG).
When the insulation layer is formed using the low-k material, the insulation layer may be easily damaged by plasma in a subsequent dry etching process. Furthermore, the insulation layer formed using the low-k material may have porosity. A porous insulation layer easily absorbs moisture through pores so that the porous insulation layer may be deteriorated. Thus, a passivation layer is generally formed on the insulation layer to prevent deterioration of the insulation layer. The passivation layer may be formed using silicon carbonitride (SiCN), silicon nitride (SiN) or silicon carbide (SiC). The passivation layer may be used as a capping layer formed on a conductive material.
Various processes are generally performed for manufacturing a semiconductor device. An inspection process is performed between processes to check a processed wafer. For example, when processing a wafer, a dummy wafer is also introduced in each process. After each process is performed, a thickness of a layer and characteristics of the layer are estimated using the dummy wafer.
While the once-used dummy wafer may be discarded, it is preferable for economic reasons to recycle the dummy wafer. As a wafer having a diameter of about 300mm has recently been used in a semiconductor manufacturing process, the desire to recycle and reuse the dummy wafer has increased.
In forming of the low-k layer and/or the passivation layer, the dummy wafer is used along with the processing wafer. After the inspection process is performed on the dummy wafer, the low-k layer and/or the passivation layer are advantageously removed from the dummy wafer.
The low-k layer and/or the passivation layer are generally removed by a dry etching process or a wet etching process. The dry etching process is performed using plasma and the wet etching process is performed using an etching solution. For example, U.S. Pat. No. 6,890,391 discloses a method of removing a low-k layer and a passivation layer using a dry etching process. In the method, the low-k layer is formed using silicon oxide, methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), silicon oxycarbide (SiOC) or carbon-doped silicon oxide (SiOCH), and the passivation layer is formed using silicon nitride (SiN) or silicon carbonitride (SiCN). Japanese Laid-Open Patent Publication No. 2001-65459 discloses a method of dry etching a low-k layer including silicon oxycarbide (SiOC) using a mixture gas including a fluorinated carbon gas, nitrogen gas, and an inert gas having at least about 80% of a flow rate based on the total gas flow rate. In addition, Korean Laid-Open Patent Publication No. 2004-102981 discloses a method of removing an insulating interlayer through a plasma etching process using a mixture gas of CF4, O2 and Ar. In the method, the insulating interlayer includes an oxide layer, an organic low-k layer, an organic porous low-k layer or a combination thereof.
In the above methods of removing the low-k layer and/or a passivation layer through a dry etching process, plasma having a high energy can cause damage to an underlying layer. Furthermore, recycling the dummy wafer using the dry etching process is not economically advantageous.
Korean Laid-Open Patent Publication No. 2002-55888 discloses a method of manufacturing a metal wiring and a capacitor in a semiconductor device. In the method, an insulation layer formed using silicon oxide, fluorinated silicate glass (FSG), carbon-doped silicon oxide (SiOCH), silicon oxycarbide (SiOC) or hydrogenated silicon oxide (SiOH), is removed using a hydrofluoric acid solution. However, the hydrofluoric acid solution does not sufficiently remove the low-k material from an object. Furthermore, the hydrofluoric acid solution only minimally etches a passivation material such as silicon carbonitride (SiCN).
Japanese Laid-Open Patent Publication No. 2005-167181 discloses a method of selectively etching a low-k layer that includes black diamond. In the method, the low-k layer is removed using an etching solution that includes about 0.5 to about 20 percent by weight of hydrofluoric acid and/or a salt thereof, about 60 to about 99.5 percent by weight of sulfuric acid and about 0 to about 20 percent by weight of water. The etching solution is reported to effectively remove the low-k layer. However, the etching solution includes an excessive amount of sulfuric acid so that an etching rate is not easily controlled, and a substrate such as a silicon wafer may be damaged.